Method of fabricating a semiconductor device

ABSTRACT

One method includes fabricating a semiconductor device including providing a dielectric layer. At least one semiconductor chip is provided defining a first surface including contact elements and a second surface opposite to the first surface. The semiconductor chip is placed onto the dielectric layer with the first surface facing the dielectric layer. An encapsulant material is applied over the second surface of the semiconductor chip in a reel-to-reel process.

BACKGROUND

The present invention relates to a method of fabricating a semiconductordevice.

Semiconductor chips include contact pads of contact elements on one ormore of their surfaces. When fabricating a semiconductor device, inparticular when housing the semiconductor chip in a semiconductor chippackage, the contact pads of the semiconductor chip have to be connectedto external contact elements of the semiconductor chip package. Forproducing semiconductor devices, a plurality of chips is provided, andthe chips are embedded in an encapsulation material to form an embeddedsubstrate. Afterwards the semiconductor chips are separated from eachother to obtain a respective plurality of semiconductor devices.

For these and other reasons there is a need for the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of embodiments and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments andtogether with the description serve to explain principles ofembodiments. Other embodiments and many of the intended advantages ofembodiments will be readily appreciated as they become better understoodby reference to the following detailed description. The elements of thedrawings are not necessarily to scale relative to each other. Likereference numerals designate corresponding similar parts.

FIG. 1 illustrates a flow diagram of a method of fabricating asemiconductor device according to one embodiment.

FIGS. 2A-C illustrate schematic cross-sectional representations ofintermediate products and a semiconductor device for illustrating oneembodiment of a method of fabricating a semiconductor device.

FIG. 3 illustrates a flow diagram of a method of fabricating asemiconductor device according to one embodiment.

FIGS. 4A-D illustrate schematic cross-sectional representations ofintermediate products and a semiconductor device for illustrating oneembodiment of a method of fabricating a semiconductor device.

FIG. 5 illustrates a flow diagram of a method of fabricating asemiconductor device according to one embodiment.

FIGS. 6A-C illustrate schematic cross-sectional representations ofintermediate products and a semiconductor device for illustrating oneembodiment of a method of fabricating a semiconductor device.

FIG. 7 illustrates a flow diagram of a method of fabricating asemiconductor device according to one embodiment.

FIGS. 8A-C illustrate schematic cross-sectional representations ofintermediate products and a semiconductor device for illustrating oneembodiment of a method of fabricating a semiconductor device.

FIG. 9 illustrate a schematic cross-sectional representation of anapparatus for carrying out a method of fabricating a semiconductordevice according to one embodiment.

FIG. 10 illustrate a schematic cross-sectional representation of anapparatus for carrying out a method of fabricating a semiconductordevice according to one embodiment.

FIG. 11A-C illustrate a schematic cross-sectional representation of anapparatus for carrying out a method of fabricating a semiconductordevice according to one embodiment.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top,”“bottom,” “front,” “back,” “leading,” “trailing,” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments can be positioned in a number of differentorientations, the directional terminology is used for purposes ofillustration and is in no way limiting. It is to be understood thatother embodiments may be utilized and structural or logical changes maybe made without departing from the scope of the present invention. Thefollowing detailed description, therefore, is not to be taken in alimiting sense, and the scope of the present invention is defined by theappended claims.

It is to be understood that the features of the various exemplaryembodiments described herein may be combined with each other, unlessspecifically noted otherwise.

In addition, while a particular feature or aspect of one embodiment maybe disclosed with respect to only one of several implementations, suchfeature or aspect may be combined with one or more other features oraspects of the other implementations as may be desired and advantageousfor any given or particular application. Furthermore, to the extent thatthe terms “include”, “have”, “with” or other variants thereof are usedin either the detailed description or the claims, such terms areintended to be inclusive in a manner similar to the term “comprise”. Theterms “coupled” and “connected”, along with derivatives may be used. Itshould be understood that these terms may be used to indicate that twoelements co-operate or interact with each other regardless whether theyare in direct physical or electrical contact, or they are not in directcontact with each other. Also, the term “exemplary” is merely meant asan example, rather than the best or optimal. The following detaileddescription, therefore, is not to be taken in a limiting sense, and thescope of the present invention is defined by the appended claims.

The embodiments of a method of fabricating a semiconductor device andthe embodiments of a semiconductor device may use various types ofsemiconductor chips or semiconductor substrates, among them logicintegrated circuits, analog integrated circuits, mixed signal integratedcircuits, sensor circuits, MEMS (Micro-Electro-Mechanical Systems),power integrated circuits, chips with integrated passives, discretepassives and so on. In general the term “semiconductor chip” as used inthis application can have different meanings one of which is asemiconductor die or semiconductor substrate including an electricalcircuit.

In several embodiments layers are applied to one another or materialsare applied or deposited onto layers. It should be appreciated that anysuch terms as “applied” or “deposited” are meant to cover literally allkinds and techniques of applying layer onto each other. In oneembodiment, they are meant to cover techniques in which layers areapplied at once as a whole, like, for example, laminating techniques, aswell as techniques in which layers are deposited in a sequential manner,like, for example, sputtering, plating, molding, chemical vapordeposition (CVD) and so on. One example for a layer to be applied is theredistribution layer (RDL). The redistribution layer can be in the formof a multilayer, in particular a multilayer including a repeating layersequence.

The semiconductor chips may include contact elements or contact pads onone or more of their outer surfaces wherein the contact elements servefor electrically contacting the semiconductor chips. The contactelements may be made from any electrically conducting material, e.g.,from a metal as aluminum, gold, or copper, for example, or a metalalloy, e.g., solder alloy, or an electrically conducting organicmaterial, or an electrically conducting semiconductor material.

The semiconductor chips may become covered with an encapsulant material.The encapsulant material can be any electrically insulating materiallike, for example, any kind of molding material, any kind of epoxymaterial, or any kind of resin material with or without any kind offiller materials. In special cases it could be advantageous to use aconductive encapsulant material. In the process of covering thesemiconductor chips or dies with the encapsulant material, fan-outembedded dies can be fabricated. The fan-out embedded dies can bearranged in an array having the form e.g., of a wafer and will thus becalled a “re-configured wafer” further below. However, it should beappreciated that the fan-out embedded die array is not limited to theform and shape of a wafer but can have any size and shape and anysuitable array of semiconductor chips embedded therein.

In the claims and in the following description different embodiments ofa method of fabricating a semiconductor device are described as aparticular sequence of processes or measures, in particular in the flowdiagrams. It is to be noted that the embodiments should not be limitedto the particular sequence described. Particular ones or all ofdifferent processes or measures can also be conducted simultaneously orin any other useful and appropriate sequence.

Referring to FIG. 1, there is illustrated a flow diagram of a method offabricating a semiconductor device according to one embodiment. Themethod includes providing a dielectric layer (s1), providing at leastone semiconductor chip defining a first surface including contactelements and a second surface opposite to the first surface (s2),placing the semiconductor chip onto the dielectric layer with the firstsurface facing the dielectric layer (s3), and applying an encapsulantmaterial over the second surface of the semiconductor chip in areel-to-reel process (s4).

A reel-to-reel process can be realized by providing a first rotatingreel, a in-run reel, a second rotating reel, a out-run reel, and aworking zone arranged between the in-run reel and the out-run reel. Thein-run reel is arranged to transport the dielectric layer with theapplied semiconductor chip to the working zone and the out-run reel isarranged to transport the dielectric layer with the appliedsemiconductor chip away from the working zone. In the working zone theencapsulant material is applied over the second surface of thesemiconductor chip. As mentioned above the measures of the flow diagramcan be conducted in another sequence. For example the semiconductorchips can also be attached to the dielectric layer during thereel-to-reel process, in particular within the working zone.

According to one embodiment the method of FIG. 1 further includesapplying the dielectric layer to a wheel before applying the encapsulantmaterial. In this embodiment the working zone is arranged at and in thevicinity of the wheel, more specifically at and in the vicinity of asurface region of the wheel along a particular circumferential angularrange of the wheel. In the working zone the dielectric layer can beapplied to the surface region of the wheel and the encapsulant materialcan be applied to the second surface of the semiconductor chip in e.g.,a dispensing zone. If appropriate a curing process and a planarizingprocess can also be carried out in the working zone as will beillustrated in further detail below.

According to one embodiment the method of FIG. 1 further includesapplying a stencil printed layer, in particular a stencil spacer, ontothe dielectric layer and applying the encapsulant material over thesecond surface of the semiconductor chip by using the stencil spacer.The stencil spacer can be of such a thickness and/or consistency that itfulfils also the function of a stiffener for stiffening the dielectriclayer.

According to one embodiment the method of FIG. 1 further includesapplying the encapsulant material by use of a squeegee. In particular inthis embodiment the applying of a stencil spacer can be useful inaddition so that the squeegee can be supported on the stencil spacer. Aswill be illustrated in further detail below, when using a wheel, e.g., arotating wheel as working zone, the squeegee can be hold stationary in adispensing zone and the encapsulant can be dispensed through thesqueegee onto the second surface of the semiconductor chip and thedielectric layer which pass along and below a lower opening of thesqueegee. The squeegee can be arranged at a particular circumferentialposition of the wheel.

According to one embodiment the method of FIG. 1 further includesprecuring or curing the obtained structure after applying theencapsulant material. In particular when using a as working zone, acuring zone can be provided at a particular circumferential position ofthe wheel. The curing zone can, for example, be arranged behind thedispensing zone in the direction of rotation of the wheel. Curing can beaccomplished by using ultraviolet light in case of an ultraviolet curingencapsulant material or, alternatively, by using infrared light or heat.

According to one embodiment the method of FIG. 1 further includesplanarizing the obtained structure after applying the encapsulantmaterial. In particular when using a as working zone, a planarizing zonecan be provided at a particular circumferential position of the wheel.The planarizing zone can, for example, be arranged behind the dispensingzone in the direction of transport on the wheel or behind the curingzone, if available.

According to one embodiment the method of FIG. 1 further includesapplying the dielectric layer to a planar moving surface before applyingthe encapsulant material. In this embodiment the working zone isprovided by a surface region of the planar moving surface and anenvironment thereof. The working zone can also include a dispensing zonein which the encapsulant material is dispensed and applied onto thesecond surface of the semiconductor chip and, if appropriate, a curingzone for precuring or curing the obtained structure after applying theencapsulant material and, if appropriate, a planarizing zone forplanarizing the obtained structure.

Referring to FIGS. 2A-C, there are illustrated schematic cross-sectionalrepresentations for illustrating one embodiment of a method offabricating a semiconductor device corresponding to the embodiment ofFIG. 1. FIG. 2A illustrates in the upper partial picture across-sectional representation of a dielectric layer 1. The dielectriclayer 1 can be made of a dielectric, insulating material which can, forexample, be comprised of a foil based on an acrylate or which can alsobe an epoxy-bistage foil. The dielectric layer 1 can, for example, alsobe made of a prepreg (preimpregnated) foil such as that known fromconventional substrate technology. The dielectric layer 1, for example,can be comprised of a photo-structurable prepreg which can be etchedafter lithographical exposure. It is also possible that the dielectriclayer 1 is made of a material that can be ablated or structured with alaser beam. The dielectric layer 1 can also include an additive, whichreleases electrically conducting material or which releases a catalyticlayer for plating upon irradiation. The dielectric layer 1 can also haveadhesion properties in order to fix semiconductor chips which are to beapplied on its surface. If, however, the dielectric layer 1 does nothave itself sufficient adhesion force at its surface, a further layer(not illustrated) including an adhesion promoter can be applied to thesurface of the dielectric layer 1. The dielectric layer 1 itself can befixed on a sacrificial carrier liner or carrier layer (not illustrated)giving mechanical rigidness for all the processing measures. Thesacrificial carrier layer can finally be simply peeled off.

FIG. 2A also illustrates in the lower partial picture a cross-sectionalrepresentation of a semiconductor chip 2 including a first surfacehaving contact elements or contact pads 2A thereon, and a second surfaceopposite to the first surface. The semiconductor chips to be used heremay be of extremely different types and may include integratedelectrical or electro-optical circuits. The semiconductor chips may be,for example, configured as power transistors, power diodes, controlcircuits, micro-processors or micro-electro-mechanical components ordiscrete passives. The semiconductor chips need not necessarily bemanufactured from specific semiconductor material and, furthermore, maycontain inorganic and/or organic materials that are not semiconductors,such as, for example, insulators, plastics or metals.

FIG. 2B illustrates a cross-sectional representation of an intermediateproduct after applying the semiconductor chip 2 to the dielectric layer1. The semiconductor chip 2 is placed onto the dielectric layer 1 withthe first surface of the semiconductor chip 2 facing the dielectriclayer 1. It is possible that the dielectric layer 1 has pre-fabricatedthrough-holes (or vias) (not illustrated) and that the semiconductorchip 2 can be placed in such a way onto the dielectric layer 1 that thecontact elements 2A of the semiconductor chip 2 are aligned with thethrough-holes of the dielectric layer 1. The semiconductor chip 2 can beplaced by different means onto the dielectric layer 1 wherein, forexample, in case of placing a plurality of semiconductor chips 2 ontothe dielectric layer 1, a pick-and-place machine can be used. A patternrecognition of the through-holes can be implemented for placing thesemiconductor chip in the correct position.

FIG. 2C illustrates a cross-sectional representation of the process ofapplying an encapsulant material 3 over the semiconductor chip 2. Theencapsulant material 3 can, for example, include a molding materialwherein the molding technique can be, for example, compression molding.The encapsulant material can also be applied by other process techniqueslike, for example, screen printing. The encapsulant materials include,for example, aliphatic and aromatic polymers including thermoplastic andthermoset type polymers and blends of these and also other various typesof polymers.

A plurality of semiconductor chips 2 is applied onto the dielectriclayer 1 and the dielectric layer 1 is supplied to an in-run rotatingreel 4. The in-run rotating reel 4 transports the dielectric layer 1 toa working zone. In another embodiment the die bonding is done in theworking zone. The working zone also includes a dispenser 6 fordispensing the encapsulant 3 on the second surfaces of the semiconductorchips 2. From the working zone the obtained structure is transported toan out-run rotating reel 8 and the out-run rotating reel 8 outputs theobtained structure, i.e. an array of semiconductor chips 2 applied ontothe dielectric layer 1 and encapsulated within the encapsulant 3. Thedielectric layer 1 and the encapsulated structure as output by theout-run rotating reel 8 can have the shape of a wafer or a rectangularshape, in particular a rectangular shape having a longitudinal sideparallel to the transport direction of the dielectric layer 1 and alateral side perpendicular to the transport direction of the dielectriclayer 1 wherein the longitudinal side is longer than the lateral side,in particular at least 10 times longer than the lateral side or in afurther embodiment quasi endless.

After encapsulating and obtaining the encapsulated array furtherprocesses will be carried out until the obtained structure can besingulated into single semiconductor devices. According to oneembodiment before singulating a conducting layer can be applied over thedielectric layer 1 wherein the conducting layer may include conductingareas which are to be aligned with the through-holes and which can beelectrically connected with the contact elements of the semiconductorchips by filling electrically conductive material into thethrough-holes. The conducting layer may include the function of aredistribution layer for redistributing the arrangement of the contactelements over a larger area. As was described above, the through-holescan be pre-fabricated in the dielectric layer 1 or they can be producedin a later process before the redistribution process. Furthermore byforming vias in the encapsulant a redistribution layer on the surface ofthe encapsulant might be applied.

According to one embodiment of the method of fabricating a semiconductordevice, the method further includes applying solder balls or solderablelands and electrically connecting the solder balls with the conductiveareas of the conductive layer and thus with the contact elements of thesemiconductor chip. According to one embodiment thereof, the methodfurther includes applying a solder resist layer, the solder resist layerincluding openings wherein the solder balls are applied above theopenings of the solder resist layer.

Typical values of the thicknesses of the layers may be as follows. Thethickness of the dielectric layer 1 typically ranges from 5 μm to 150μm, whereas the thickness of the semiconductor chip 2 typically rangesfrom 20 μm to 450 μm, and the thickness of the encapsulant materialtypically ranges from 200 μm to 800 μm. All these thickness ranges alsocover incremental values wherein the increment is 1 μm.

Referring to FIG. 3, there is illustrated a flow diagram of a method offabricating a semiconductor device according to one embodiment. Themethod includes providing a dielectric layer (s1), providing at leastone semiconductor chip defining a first surface including contactelements and a second surface opposite to the first surface (s2),placing the semiconductor chip onto the dielectric layer with the firstsurface facing the dielectric layer (s3), applying the dielectric layerto a wheel (s4), and applying an encapsulant material over the secondsurface of the semiconductor chip (s5).

According to one embodiment the method of FIG. 3 further includesapplying a stencil spacer onto the dielectric layer, and applying theencapsulant material over the second surface of the semiconductor chipby using a stencil printing process.

According to one embodiment the method of FIG. 3 further includesapplying the encapsulant material by use of a squeegee.

According to one embodiment the method of FIG. 3 further includesprecuring or curing of the obtained structure after applying theencapsulant material.

According to one embodiment the method of FIG. 3 further includesplanarizing the obtained structure after applying the encapsulantmaterial.

Referring to FIGS. 4A-D, there are illustrated schematic cross-sectionalrepresentations for illustrating one embodiment of a method offabricating a semiconductor device corresponding to the embodiment ofFIG. 3. With respect to FIGS. 4A,B reference is made to FIGS. 2A,B andthe respective description thereof.

FIG. 4C,D illustrate cross-sectional representations of applying thestructure consisting of the semiconductor chip 2 and the dielectriclayer 1 on a wheel 5, e.g., a rotating wheel (FIG. 4C) and applying anencapsulant material 3 over the semiconductor chip 2 (FIG. 4D). Theencapsulant material 3 can, for example, include a molding materialwherein the molding technique can be, for example, compression moldingor powder molding. The encapsulant material can also be applied by otherprocess techniques like, for example, screen or stencil printing. Theencapsulant materials include, for example, aliphatic and aromaticpolymers including thermoplastic and thermoset type polymers and blendsof these and also other various types of polymers.

A plurality of semiconductor chips 2 is applied onto the dielectriclayer 1 and the dielectric layer 1 is supplied to a wheel 5 and appliedto a portion of a surface thereof. The wheel 5 transports the dielectriclayer 1 to a working zone which is arranged at and in the vicinity of asurface region of the wheel 5 along a particular circumferential angularrange of the wheel 5. The working zone includes a dispenser 6 fordispensing the encapsulant 3 on the second surfaces of the semiconductorchips 2. At the end of the working zone the obtained structure isoutput, wherein the obtained structure is comprised of an array ofsemiconductor chips 2 applied onto the dielectric layer 1 andencapsulated within the encapsulant 3.

Further embodiments of the method according to FIGS. 3 and 4A-D can beprovided by combining the above with additional aspects or features ofembodiments as were described above in connection with FIGS. 1 and 2A-D.

Referring to FIG. 5, there is illustrated a flow diagram of a method offabricating a semiconductor device according to one embodiment. Themethod includes providing a dielectric layer applied with a stencilspacer (s1), providing at least one semiconductor chip defining a firstsurface including contact elements and a second surface opposite to thefirst surface (s2), placing the semiconductor chip onto the dielectriclayer with the first surface facing the dielectric layer (s3), andapplying an encapsulant material over the second surface of thesemiconductor chip by using the stencil spacer for planarizing theencapsulant material (s4).

According to one embodiment the method of FIG. 5 further includesprecuring or curing the obtained structure after applying theencapsulant material.

According to one embodiment the method of FIG. 5 further includesplanarizing the obtained structure after applying the encapsulantmaterial.

According to one embodiment the method of FIG. 5 further includesapplying the encapsulant material over the second surface of thesemiconductor chip in a reel-to-reel process.

According to one embodiment the method of FIG. 5 further includesapplying the dielectric layer to a wheel before applying the encapsulantmaterial.

According to one embodiment the method of FIG. 5 further includesapplying the encapsulant material by use of a squeegee.

According to one embodiment the stencil layer is not applied to thedielectric layer from the beginning but is rather applied to thedielectric layer as a sidewall layer simultaneously with encapsulating.In particular the sidewall layer can be applied to the dielectric layeras mold foil. More specifically it can be applied to the dielectriclayer by using a reel-to-reel process.

Referring to FIGS. 6A-C, there are illustrated schematic cross-sectionalrepresentations for illustrating one embodiment of a method offabricating a semiconductor device corresponding to the embodiment ofFIG. 5. With respect to FIGS. 6A,B reference is made to FIGS. 2A,B andthe respective description thereof. In addition the dielectric layer 1is provided with a stencil spacer 9 applied thereon. FIG. 6A (upperpart) illustrates a lateral cross-sectional representation of thedielectric layer 1 and the stencil spacer 9 applied thereon. Asillustrated the stencil spacer 9 can be deposited in the form of twostrips applied along the two opposing longitudinal side edges of thedielectric layer 1, i.e. along side edges parallel to a direction offeeding the dielectric layer 1 to a dispenser 6 for applying anencapsulant material 3 over the semiconductor chip 2.

The height of the stencil spacer 9 determines and limits the thicknessof the encapsulant layer to be deposited. In the embodiment of FIG. 6Bthe stencil spacer 9 is illustrated to have a height greater than thethickness of the semiconductor chip 2 which means that the encapsulantlayer to be deposited will have a thickness greater than the thicknessof the semiconductor chip 2. Depositing of the encapsulant can beaccomplished by using a squeegee whereas the stencil spacer 9 can serveas a mechanical support for the squeegee during the deposition process.

FIG. 6C illustrates a lateral cross-sectional representation of anintermediate product after applying of an encapsulant material 3 on thesemiconductor chip 2 and the dielectric layer 1. It can be seen that thethickness of the deposited encapsulant material layer 3 corresponds tothe height of the stencil spacer 9. Thereafter the stencil spacer 9 canbe removed, if appropriate.

Further embodiments of the method according to FIGS. 5 and 6A-C can beprovided by combining the above with additional aspects or features ofembodiments as were described above in connection with FIGS. 1 to 4.

Referring to FIG. 7, there is illustrated a flow diagram of a method offabricating a semiconductor device according to one embodiment. Themethod includes providing a dielectric layer (s1), providing at leastone semiconductor chip defining a first surface including contactelements and a second surface opposite to the first surface (s2),placing the semiconductor chip onto the dielectric layer with the firstsurface facing the dielectric layer (s3), and applying an encapsulantmaterial over the second surface of the semiconductor chip by use of asqueegee (s4).

According to one embodiment the method of FIG. 7 further includesapplying a stencil spacer onto the dielectric layer.

According to one embodiment the method of FIG. 7 further includes curingthe obtained structure after applying the encapsulant material.

According to one embodiment the method of FIG. 7 further includesplanarizing the obtained structure after applying the encapsulantmaterial.

According to one embodiment the method of FIG. 7 further includesapplying the encapsulant material over the second surface of thesemiconductor chip in a reel-to-reel process.

According to one embodiment the method of FIG. 7 further includesapplying the dielectric layer to a wheel before applying the encapsulantmaterial.

Referring to FIGS. 8A-C, there are illustrated schematic cross-sectionalrepresentations for illustrating one embodiment of a method offabricating a semiconductor device. With respect to FIGS. 8A,B referenceis made to FIGS. 2A,B and the respective description thereof.

FIG. 8C illustrates a cross-sectional representation of applying anencapsulant material 3 over the semiconductor chip 2. The encapsulantmaterial 3 is applied by use of a squeegee 10 as a dispenser of theencapsulant material 3. The squeegee 10 can, for example, be supportedon a stencil spacer (not illustrated) as outlined in the previousembodiment.

Further embodiments of the method according to FIGS. 7 and 8A-C can beprovided by combining the above with additional aspects or features ofembodiments as were described above in connection with FIGS. 1 to 6.

Referring to FIG. 9 there is illustrated a schematic cross-sectionalrepresentation of an apparatus for carrying out a method of fabricatinga semiconductor device according to one embodiment. The apparatus 100includes a wheel 15 of radius R arranged between a first rotating reel(in-run reel) 18 and a second rotating reel (out-run reel) 19. The wheel15 can be formed as a massive cylinder or it can alternatively be formedas a hollow cylinder so that suitable heating means can be arranged inthe inner hollow space of the cylinder. The upper surface of the wheel15 and the region above the upper surface form a working zone in which afed in layered structure can be processed in a predetermined manner.From the left side a layered structure can be fed into the apparatus 100to be processed in a manner described further below.

The layered structure fed into the apparatus 100 can have a form likethat illustrated in FIG. 6B, which consists of a dielectric layer 1 witha plurality of semiconductor chips 2 applied thereon and a stencilspacer 9 in the form of strip layers applied on longitudinal edgeportions of the dielectric layer 1 and/or on a carrier liner (notillustrated) supporting the dielectric layer 1. As the dielectric layer1 can be in the form of a thin flexible foil, the stencil spacer 9 inaddition acts as a stiffener giving the layered structure hold andstability. When such a layered structure is fed into the inner spacebetween the first rotating reel 18 and the wheel 15, the layeredstructure is gripped and pulled onto the upper surface of the wheel 15.

The working zone of the apparatus 100 may include a first zone forsemiconductor chip placement in case that the chips were not yet appliedto the dielectric layer 1. The working further includes a dispensingzone 20 for dispensing an encapsulant onto the second upper surfaces ofthe semiconductor chips 2 and the dielectric layer 1. The dispensingzone 20 can include a stationary squeegee 21 being positioned such thata front edge thereof rests on the stencil spacer 9 of the layeredstructure. The squeegee 21 includes a dispense channel 22 for deliveringthe encapsulant material 23 at a lower opening of the dispense channel22. Thus the squeegee 21 distributes the encapsulant 23 and thethickness of the encapsulant layer is defined by the position of thesqueegee 21 which itself is defined by the height of the stencil spacer9 supporting the squeegee 21.

The working zone of the apparatus 100 further includes a curing zone 30for precuring/curing or hardening the encapsulant 3. The curing zone 30is arranged at a circumferential position behind the dispensing zone 20in the transport direction of the wheel 15. The curing zone 30 caninclude a conventional tunnel oven or an IR oven. In case of using an UVcuring encapsulant the curing zone 30 can include one or more UV lightsources.

The working zone of the apparatus 100 might further include aplanarizing zone 40 for planarizing the encapsulated structure. Theplanarizing zone 40 can include a knife, a knife-edge 41 or a grindingwheel arranged laterally with respect to the encapsulated structure andhaving a length equal to or greater than the lateral width of theencapsulated structure. Alternatively the upper surface of the structurecan be grinded or polished in a separate process after being output fromthe apparatus 100.

The layered structure is output by a second rotating reel 19 (out-runreel). In the described embodiment the encapsulated product has a quasiendless form or an intermediate rectangular form having a longitudinalside which is considerably longer than the lateral side, in particular afactor of 10 or more longer than the lateral side. After releasing theencapsulated product from the apparatus 100, some more processes will becarried out like depositing a redistribution layer/layers on thebackside of the dielectric layer 1, connecting conductive areas of theredistribution layer with contact pads of the semiconductor chips andapplying a solder resist layer and solder balls electrically connectedwith the conductive areas of the redistribution layer. Furthermorethrough encapsulant vias, a redistribution layer/layers on the surfaceof the encapsulant might be applied. Additional solder ball or landsmight be applied on the encapsulant side. At the end the panel will besingulated into a plurality of semiconductor package devices.

The wheel 15 can be a rotating wheel or a stationary wheel or astationary or moving substrate block (with e.g., different curvatures intransport direction or perpendicular to the transport direction atdifferent working stations) wherein the layered structure is slidinglymoved over the surface. In the case of a stationary block the surfacemight be also planar (R=∞) and the zones, namely the dispensing zone,the curing zone and the planarizing zone are arranged linearly. In thecase of curvatures it is also possible to select the radius R in a waythat possible warpage of the layered structure can be compensated in anoptimal way. Warpage can occur when different components of the layeredstructure, for example the dielectric layer 1 and the semiconductorchips have different thermal expansion coefficients or when theencapsulant illustrates a particular shrinkage when curing. In thisrespect it is also possible theoretically to provide for an upwardcurvature of the wheel in order to compensate for possible warpage orshrinkage effects of the layered structure. This upward curvature willthen be taken into account in the design of the squeegee so that adesired height of the semiconductor package can be obtained.

The wheel 15 can also be replaced/covered by an endless circulatingbelt, in particular a belt fabricated by stainless steel to avoidrelative motion between the structured layers and the wheel.

Referring to FIG. 10 there is illustrated a method of fabricating asemiconductor device according to one embodiment. This method includesproviding a dielectric layer, providing at least one semiconductor chipdefining a first surface including contact elements and a second surfaceopposite to the first surface, placing the semiconductor chip onto thedielectric layer with the first surface facing the dielectric layer;

applying a sidewall layer onto the dielectric layer, and

applying an encapsulant material over the second surface of thesemiconductor chip.

In the embodiment illustrated in FIG. 10, an apparatus 200 is arrangedsuch that the stencil spacer is applied to the dielectric layervirtually simultaneously with the applying of the encapsulant. To thispurpose two additional rotating reels 26 and 27 are provided for feedinga foil 28, in particular a mold foil, to the wheel 15. The foil 28 canbe formed with side strips as illustrated in cross section in FIGS. 6A-Cincluding substantially two strips to be applied such that they extendalong the longitudinal side edges of the dielectric layer 1 to prevent alateral outflow of the encapsulant. Within the foil 28 the longitudinalstrips can be interconnected by lateral bars or tape/tapes. The moldfoil 28 can be removed later, e.g., after the precuring/curing processor it can also be retained as part of the final semiconductor package.

A dispenser 60 is provided to dispense the encapsulant onto thedielectric layer 1 and the semiconductor chips. The dispenser 60 isdirected substantially to the location where the foil is deposited tothe dielectric layer 1. Lateral outflow of the encapsulant is preventedby the side strips of the foil 28. The height of the encapsulant layeris determined by the position of the rotating reel 27 and its distanceto the wheel 15. In case of the dielectric layer having the stencilspacer a simple planar foil 28 might be used. Instead of dispensing theencapsulant a laminate of an encapsulant material can also be depositedonto the dielectric layer 1 whereas in addition an adhesion promotercould be applied to improve the adhering of the laminate to thedielectric layer 1 and the semiconductor chips 2.

Referring to FIGS. 11A-C there is illustrated a method of fabricating asemiconductor device according to one embodiment. Such method offabricating a semiconductor device includes providing a dielectriclayer, providing at least one semiconductor chip defining a firstsurface including contact elements and a second surface opposite to thefirst surface, placing the semiconductor chip onto the dielectric layerwith the first surface facing the dielectric layer, applying a dam ontothe dielectric layer, and applying an encapsulant material over thesecond surface of the semiconductor chip.

FIG. 11A illustrates a schematic cross-sectional representation of oneembodiment of an apparatus for carrying out the method. For simplicityin the embodiment as illustrated in FIG. 11A all stations are depictedin a line. In this embodiment the apparatus 300 is arranged such that atfirst a dam 70 is applied onto the dielectric layer 1 and curedafterwards, e.g., by UV exposure in case of an UV curing material usedas material for the dam. The dam 70 prevents lateral outflow of theencapsulant applied later onto the dielectric layer 1. FIG. 11B depictsa sectional view at the line A-A showing the dielectric layer 1, thesemiconductor chips 2 and the dam 70 formed of two strips deposited atthe longitudinal side edges of the dielectric layer 1. Then theencapsulant material is dispensed and filled into the space formed bythe dielectric layer 1 and the dam 70. FIG. 11C depicts a sectional viewat the line B-B showing the dielectric layer 1, the semiconductor chips2, the dam 70 and the encapsulant 80. The exact thickness or height ofthe encapsulant can be adjusted in a following planarizing process,e.g., by using a knife, a knife-edge 90 or grinding wheel, oralternatively in a polishing or grinding process after release of theobtained structure out of the apparatus 300.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

1. A method of fabricating a semiconductor device, comprising: providinga dielectric layer; providing at least one semiconductor chip defining afirst surface comprising contact elements and a second surface oppositeto the first surface; placing the semiconductor chip onto the dielectriclayer with the first surface facing the dielectric layer; and applyingan encapsulant material over the second surface of the semiconductorchip in a reel-to-reel process.
 2. The method of claim 1, furthercomprising: applying the dielectric layer to a wheel before applying theencapsulant material.
 3. The method of claim 1, further comprising:applying a stencil spacer onto the dielectric layer; and applying theencapsulant material over the second surface of the semiconductor chipby using the stencil spacer.
 4. The method of claim 1, furthercomprising: applying the encapsulant material by use of a squeegee. 5.The method of claim 4, further comprising: precuring and/or curing theobtained structure after applying the encapsulant material.
 6. Themethod of claim 1, further comprising: the dielectric layer is supportedby a carrier which is removed later.
 7. A method of fabricating asemiconductor device, comprising: providing a dielectric layer;providing at least one semiconductor chip defining a first surfacecomprising contact elements and a second surface opposite to the firstsurface; placing the semiconductor chip onto the dielectric layer withthe first surface facing the dielectric layer; applying the dielectriclayer to a wheel; and applying an encapsulant material over the secondsurface of the semiconductor chip.
 8. The method of claim 7, furthercomprising: applying a stencil spacer onto the dielectric layer; andapplying the encapsulant material over the second surface of thesemiconductor chip by using a stencil printing process.
 9. The method ofclaim 7, further comprising: applying the encapsulant material by use ofa squeegee.
 10. The method of claim 7, further comprising: precuringand/or curing of the obtained structure after applying the encapsulantmaterial.
 11. The method of claim 7, further comprising: the dielectriclayer is supported by a carrier which is removed later.
 12. A method offabricating a semiconductor device, comprising: providing a dielectriclayer applied with a stencil spacer; providing at least onesemiconductor chip defining a first surface comprising contact elementsand a second surface opposite to the first surface; placing thesemiconductor chip onto the dielectric layer with the first surfacefacing the dielectric layer; and applying an encapsulant material overthe second surface of the semiconductor chip by using the stencil spacerfor planarizing the encapsulant material, and using a reel-to-reelprocess to apply the encapsulant material, including performing thereel-to-reel process by using a first reel and a second reel and aworking zone arranged between the first and second reels and that thedielectric layer is fed into the working zone by the first reel and isfed away from the working zone by the second reel, and wherein theworking zone comprises a wheel having a downward or upward curvature ora block having a planar surface.
 13. The method of claim 12, furthercomprising: precuring and/or curing the obtained structure afterapplying the encapsulant material.
 14. (canceled)
 15. The method ofclaim 12, further comprising: applying the dielectric layer to a wheelbefore applying the encapsulant material.
 16. The method of claim 12,further comprising: applying the encapsulant material by use of asqueegee.
 17. The method of claim 12, further comprising: the dielectriclayer is supported by a carrier which is removed later.
 18. The methodof claim 12, further comprising: applying the stencil layer to thedielectric layer as a mold foil.
 19. The method of claim 18, furthercomprising: applying the mold foil in a reel-to-reel process.
 20. Amethod of fabricating a semiconductor device, comprising: providing adielectric layer; providing at least one semiconductor chip defining afirst surface comprising contact elements and a second surface oppositeto the first surface; placing the semiconductor chip onto the dielectriclayer with the first surface facing the dielectric layer; and applyingan encapsulant material over the second surface of the semiconductorchip by use of a squeegee, and using a reel-to-reel process, includingperforming the reel-to-reel process by using a first reel and a secondreel and a working zone arranged between the first and second reels andthat the dielectric layer is fed into the working zone by the first reeland is fed away from the working zone by the second reel, and whereinthe working zone comprises a wheel having a downward or upward curvatureor a block having a planar surface.
 21. The method of claim 20, furthercomprising: applying a stencil spacer onto the dielectric layer. 22.(canceled)
 23. The method of claim 20, further comprising: thedielectric layer is supported by a carrier which is removed later.
 24. Amethod of fabricating a semiconductor device, comprising: providing adielectric layer; providing at least one semiconductor chip defining afirst surface comprising contact elements and a second surface oppositeto the first surface; placing the semiconductor chip onto the dielectriclayer with the first surface facing the dielectric layer; applying a damonto the dielectric layer; and applying an encapsulant material over thesecond surface of the semiconductor chip, wherein a reel-to-reel processis used to apply the encapsulant material, wherein the reel-to-reelprocess is performed by using a first reel and a second reel and aworking zone arranged between the first and second reels and that thedielectric layer is fed into the working zone by the first reel and isfed away from the working zone by the second reel, and wherein theworking zone comprises a wheel having a downward or upward curvature ora block having a planar surface.
 25. The method of claim 24, furthercomprising: the dielectric layer is supported by a carrier which isremoved later.
 26. A method of fabricating a semiconductor device,comprising: providing a dielectric layer applied with a stencil spacer;providing at least one semiconductor chip defining a first surfacecomprising contact elements and a second surface opposite to the firstsurface; placing the semiconductor chip onto the dielectric layer withthe first surface facing the dielectric layer; applying the stencillayer to the dielectric layer as a mold foil; wherein the mold foil isfed to the dielectric layer by a first reel and a second reel; andapplying an encapsulant material over the second surface of thesemiconductor chip by using the stencil spacer for planarizing theencapsulant material.
 27. A method of fabricating a semiconductordevice, comprising: Providing a dielectric layer; providing at least onesemiconductor chip defining a first surface comprising contact elementsand a second surface opposite to the first surface; placing thesemiconductor chip onto the dielectric layer with the first surfacefacing the dielectric layer; applying a dam onto the dielectric layer;curing the dam; applying an encapsulant material over the second surfaceof the semiconductor chip; and curing the encapsulant material.